This invention relates to high density non-volatile memory, and specifically to a cross-point memory array incorporating ferroelectric, colossal magnetoresistive-based resistors, and a ferroelectric, colossal magnetoresistive-based resistors having a p/n junction therein.
An ongoing goal of IC designers is the provision of a memory cell having a very small size, low power and current programming requirements, and long charge retention. A number of IC memory devices are known. A flash memory requires one transistor per memory cell and also requires high programing voltages. This type of non-volatile memory is not suitable for low-power, high-speed application. A ferroelectric-based RAM also requires a single transistor per memory cell, however, known FeRAMs have a relatively short charge retention time, on the order of nano-seconds. There are also problems associated with nano-scale structures when it is required to apply photoresist and to etch the structure. A MRAM requires high current to program data into the memory cell.
Fabrication of nano-scale (10xe2x88x929 meters) ICs is limited by the resolution of the lithography portion of the fabrication process, which is approximately 0.1 xcexcm (10xe2x88x927 meters). E-beam lithography may able to define line width as narrow as 0.01 xcexcm (10xe2x88x928 meters), however, the through put is very slow. A manufacturing process having the reliability and throughput of conventional lithography and etching with nearly the resolution of E-beam lithography is therefore desirable.
Liu et al. Electrical-pulse-induced reversible resistance change effect in magnetoresistive films, Applied Physics Letters, Vol.76, #19, p.2749, May, 2000, describes use of colossal magnetoresistive (CMR) films in memory devices.
A method of fabricating a nano-scale resistance cross-point memory array includes preparing a silicon substrate; depositing silicon oxide on the substrate to a predetermined thickness; forming a nano-scale trench in the silicon oxide; depositing a first connection line in the trench; depositing a memory resistor layer in the trench on the first connection line; depositing a second connection line in the trench on the memory resistor layer, and completing the memory array.
A cross-point memory array includes a silicon substrate; a first connection line formed on the substrate; a colossal magnetoresistive layer formed on the first connection line; a silicon nitride layer formed on a portion of the colossal magnetoresistive layer; and a second connection line formed adjacent the silicon nitride layer and on the colossal magnetoresistive layer.
It is an object of the invention to provide a nano-scale non-volatile memory array for ultra-high density low power consumption memory array.
Another object of the invention is to provide a method of fabricating a nano-scale non-volatile memory array for ultra-high density low power consumption memory array.
Another object of the invention is to provide a memory cell of size 1F2, where F is the minimum feature size of lithographic resolution.
A object of the invention is to provide a memory cell having a 0.1 xcexcm node is a cell area of 0.01 xcexcm2.
A further object of the invention is provide a memory array having a P+N diode at every memory cell to prevent read interference.
This summary and objectives of the invention are provided to enable quick comprehension of the nature of the invention. A more thorough understanding of the invention may be obtained by reference to the following detailed description of the preferred embodiment of the invention in connection with the drawings.